作者nc23nick (弄牛连)
看板Electronics
标题[请益] Verilog module reset写法 2
时间Sat Dec 3 15:45:06 2016
延续之前小弟在版上发问的问题，how to reset counter in state of FSM ?
小弟在top module 里新增一条讯号线clear来reset state里的counter
现在问题来了modelsim output waveform一切正常，但用ise烧fpga
吐出的波形在第一次clear触发後讯号就都错出(疑是control没有被reset)
想请问大大小弟下面的写法是否有误?
top.m
===================================================================
always @(posedge clk or negedge rst) begin // reset control of unit
if (~rst) begin
clear <= 0;
end
else if (curr_state == S4 && counter == 10'd127 ||
curr_state == S5 && counter == 10'd236 || ) begin
clear <= 1;
end
else begin
clear <= 0;
end
end
===================================================================
state4.m
===================================================================
always @(posedge clk or negedge rst) begin
if(~rst) begin
control= 1;
set = 0;
end
else begin
if(set == 0) begin
control = 0;
set = 1;
end
else
control = (clear == 1) ? 0 : control + 1;
end
end
===================================================================
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※ 编辑: nc23nick (36.232.134.192), 12/03/2016 15:46:50
1F：→ r901042004: 多加一个state专门用来把counter归零应该比较简单，你 12/03 17:28
2F：→ r901042004: 的counter次数这麽多应该不差一个clk吧？ 12/03 17:28