作者gecer (gecer)
看板Electronics
标题[问题] Verilog syntax error
时间Sat Nov 2 09:18:55 2019
小弟目前 verilog 语法问题 题目如下
Create 16 D flip-flops. It's sometimes useful to only modify parts of a group
of flip-flops. The byte-enable inputs control whether each byte of the 16
registers should be written to on that cycle. byteena[1] controls the upper
byte d[15:8], while byteena[0] controls the lower byte d[7:0].
resetn is a synchronous, active-low reset.
All DFFs should be triggered by the positive edge of clk.
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always@(posedge clk) begin
if (~resetn) begin
q=8'b00000000;
end
else begin
case (byteena)
2'b1X: assign q[15:8] = d[15:8];
2'bX1: assign q[7:0] = d[7:0];
endcase
end
end
endmodule
问题在case 的部分 compile error
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※ 编辑: gecer (122.121.17.136 台湾), 11/02/2019 09:21:37
1F：推 tkhan: 这不是C吗？ 11/02 09:21
2F：→ r901042004: assign不能加在always内.. 11/02 09:42
3F：→ r901042004: 如果case想要用don't care的话，请善用casez + ? 11/02 09:47
4F：推 r901042004: DFF的assignment最好用nonblocking (<=) 11/02 09:54
5F：→ r901042004: 这题使用part-select会更简洁 11/02 09:55
6F：推 www85109: don’t care应该用 casex 且blocking 改成 non-blocking 11/02 12:09
7F：推 xoverspeed: 发现还有resetn是16’b0～～ 11/03 14:31