作者lwtistunning (考验)
看板Grad-ProbAsk
标题[理工] [计组]-95 台大资工
时间Thu Oct 29 19:01:38 2009
ADDI r1，r0，#101
ADDI r2，r0，A
Loop:LD r3，0(r2)
ADDI r3，r3，#1
SD r3，0(r2)
ADDI r2，r2，#4
SUBI r1，r1，#1
BNE r1，r0，Loop
Assume that the branch is resolved during the instruction decode stage,
and full register forwarding are implemented.
Assume that all memory reference hit in the cache and TLBs.
the pipeline does not implement any branch prediction mechanism.
How many stall cycle are in one loop iteration including stalls caused
by the branch instruction?
我想问的是 SUBI r1，r1，#1
BNE r1，r0，Loop 这两指令中 明显有data hazard存在
题目说有支援forwarding，那不就应该靠forwarding就能解决这边的data hazard了吗?
解答却是说，需要在这两道指令中再加一个stall才可。
有人能教我一下为什麽这边还要stall一个clock呢?
(解答这样说；Since branch decision is resolved during ID stage,a clock stall is
needed between SUBI and BEQ.)
因为我在做其它考古题时，也有遇到类似情形，但如果有支援forwarding下
都是不用再加一个stall的。
例如中央97的一题 or $3，$2，$1
beq $2，$3，loop 显然也有data hazard存在
但解答是说用forwarding即可解。
难道是有提到branch decision is resolved during ID stage.
那麽即使在有支援forwarding下，还是要stall一个clock??
麻烦各位指导一下，还是我观念有错? 谢谢!!
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※ 编辑: lwtistunning 来自: 220.139.133.70 (10/29 19:09)