课程名称︰类比积体电路设计 课程性质︰系订选修 课程教师︰刘深渊 开课学院：电资学院 开课系所︰电机系 考试日期（年月日）︰2009.4.14 考试时限（分钟）：120 是否需发放奖励金：是，谢谢 （如未明确表示，则不予发放） 试题 : 1. Describe the basic processing steps to realize the CMOS devices(10%). 2. To realize an NMOS device, two of the steps are realizing n+ regions (drain or sources for an NMOS device) and realizing its poly gate. Which step should be performed first? Why? (5%) (原题目有误,上述为老师修改过後的题目) 3.(a) Draw a cross section of an NMOS with p-substrate (5%). (b) Describe all the parasitic capacitances for (a) in triode region and saturaion regions. (10%) (c) Plot the small-signal model of an NMOS including the parasitic capacitance. (10%) (d) Describe the second-order effects for a MOS device. (10%) (e) Describe three layout schemes to match two wide-width devices. (5%) (f) Plot the layout of two matched capacitors with the ratio of 1:8. (5%) (g) Describe what is the CMRR and its definition. (5%) 4.(a) Calculate the transfer function of Fig.1(a) by using Fig.1(b). (10%) (b) Calculate the input impedance of Fig.1(a) from the node X to the right direction. (10%) (注:本题图请参考课本P.178 Fig 6.17) 5.(a) Calculate the transfer function by using the simplified high-frequency model of the differential pair in Fig.2. (5%) (assume ro3>>1/gm3, and ro1 = ro2) (b) If the current mirror pole is much higher than the output pole, please calculate the poles from (a). (10%) (注:本题图请参考课本P.191 Fig.6.31(a)) 课本: Behzad Razavi, "Design of Analog CMOS Integrated Circuits" --

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